1. Field of the Invention
The present invention relates to a semiconductor device fabrication process; and more particularly, to a method of forming a dual damascene wiring pattern.
2. Prior Art of the Invention
Wiring structures using a dual damascene configuration in deep sub-micron integrated circuit devices have become widespread in use. FIGS. 1A through 1E are sectional views illustrating a universally popular dual damascene process.
Referring to FIG. 1A, in a via photolithography process, a copper layer 20 as an electric connection layer is formed on a portion of an upper surface of a substrate 10 on which semiconductor devices are formed. An etch stop film 30 and an interlayer dielectric film ILD 40 of the SiOC:H group are formed on the substrate 10 and the copper layer 20. On the interlayer dielectric film 40 a photoresist is deposited, and a photolithographic process for forming a via hole having a predetermined size D1 is executed. During the photolithographic process, a photoresist pattern 50 is formed as shown in FIG. 1A. A dry etch is performed on the resultant structure of FIG. 1A to form a via hole 60 as a primary opening as shown in FIG. 1B. The residual photoresist 50 used as an etch mask is removed by an ashing process after the completion of the via etch process.
FIG. 1C represents a trench photolithography process of forming a secondary opening having a width D2 larger than that of the via hole 60 of FIG. 1B. FIG. 1D illustrates a trench etch process that follows the trench photo process. As a result, the openings 60, 80 having two different widths are formed in the ILD 40 body. After executing the process of FIG. 1D, an ashing process is performed to achieve the resulting dual damascene structure shown in FIG. 1E.
In the conventional dual damascene process, the size of the primary via opening 60 is preserved, even in the case where a misalignment occurs during the photo process of FIG. 1C for forming the trench 80 that is executed following the etch of the via hole. However, in the case where a SiOC:H group material is used for the interlayer dielectric film ILD 40, the etch stop film 30, or etch stopper 30, formed under the interlayer dielectric 40 can become seriously damaged during the via etch process. The major cause for the serious damage of the etch stop film 30 is raised by a comparatively lower etch selection rate between the interlayer dielectric film 40 and the etch stop film 30. In the case where the etch stop film 30, made of SiN or SiC etc., is etched excessively, the copper layer 20 that provides an electrical connection layer formed under the etch stop layer 30 is influenced by the etch damage. Further, in the case where the photoresist inside the via hole inside is not completely eliminated in the trench photo process following the via etch process, a “fence” can be generated following the trench etch process, owing to photoresist material that remains within the via hole. Such etching damage and the fence adversely affect production yield and resulting device reliability. Meanwhile, in the trench photoresist coating process following the via etch, a phenomenon can occur that results in a photoresist coating thickness that is not uniform as a result of via density. In such a case, the condition of the photo process is changed, to thus cause partial pattern inferiority.
In the conventional process recently developed to address the above problems, as shown in FIGS. 2A through 2F, a method has become popular that involves forming a bottom anti-reflection coating (BARC) film 65 is filled into the via hole 60 partially or completely and an etch back process is then performed. The steps of FIGS. 2A through 2F excepting FIG. 2C are the same as FIGS. 1A through 1E in their processes. FIG. 2C shows the structure following introduction of the BARC film 65.
The BARC film 65 protects the etch stop film 30 as the etch stopper when executing the trench etch. The conventional approach shown in FIGS. 2A through 2F however introduces the additional problem that photo margin becomes very small in the following trench photo patterning process due to the height of the BARC film 65 in the via hole 60. If the height of the BARC film 65 is increased in order to improve the photo margin, the fence problem can still occur after the trench etch process.